Domain Specific Languages (DSLs) have the potential to revolutionize the development of scientific high-performance software by providing scientists with abstractions that are tailored for their specific problem. By encoding rich domain knowledge by the programmer, the compilation tool-chain is then able to make effective choices around parallelism. Furthermore, if designed correctly, then the programmer is able to express their workload in an architecture-independent fashion, thus making portability across architectures possible, with the compilation tool-chain doing much of the heavy lifting.

This is especially important in HPC as even effectively exploiting today’s supercomputers is fraught will difficulty and in the domain of the few experts. As we move towards exascale, with increasingly complex heterogeneous systems, the ability to fully exploit these machines will be beyond even the most experienced guru. Put simply, the languages and technologies that are currently ubiquitous in HPC (C, Fortran, MPI, OpenMP, CUDA) are too low level for end-user programming and the abstraction level needs to be raised.

The term “language” in DSLs can be a bit of a misnomer, as the name of the game here is raising the abstraction level, and consequently technologies such as abstractions embedded inside existing languages, frameworks and libraries are also highly topical. Many believe that DSLs have the potential to get us closer to achieving the three P’s; productivity, performance, and performance portability. Whilst historically this objective has been often seen as somewhat of a chimera, there is wide acceptance in the HPC community that we need to solve the programming challenges associated with future exascale machines. Furthermore, there is a growing consensus that the benefits that DSLs can deliver are paramount and could be critical in unlocking the full potential of future supercomputers.


The workshop will be held in the Hugh Fraser room and running between 9:00am and 12:30pm on Monday 22nd of August.

Time Title Presenter
9:00 - 9:05 Session welcome and aims Nick Brown
9:05 - 9:40 Keynote: Evolutionary Re-Engineering of an Industrial HPC application with OP2 (Abstract) Gihan Mudalige
9:40 - 10:05 Research paper: Performance of the Vipera framework for DSLs on micro-core architectures (Abstract) Maurice Jamieson
10:05 - 10:30 Research paper: FFTc: An MLIR Dialect for Developing HPC Fast Fourier Transform Libraries (Abstract) Yifei He
10:30 - 11:00 Morning coffee break  
11:00 - 11:25 Invited talk: xDSL an ecosystem for DSL development (Abstract) Tobias Grosser
11:25 - 11:50 Research paper: TensorFlow as a DSL for stencil-based computation on the Cerebras Wafer Scale Engine (Abstract) Nick Brown
11:50 - 12:25 Panel session  
12:25 - 12:30 Conclusions and next steps Nick Brown